A spread spectrum communication system is represented by the following equation:
      s    ⁡          (      t      )        =            ∑              i        =        1            M        ⁢                  ⁢          (                                    a            i                    ⁡                      (                          t              -                              τ                i                                      )                          -                  c          ⁡                      (                          t              -                              τ                i                                      )                              )      wherein                s (t): spread-spectrum and multiplexed signal to be transmitted,        ai (t): data to be transmitted having been serial-parallel converted by a number of signals in multiplexing and not yet have the spectrum spread,        c (t): spreading code sequence (having a period of 1/spreading code sequence length relative to the period in variation of ai (t),        M: number of signals in multiplexing, and        τi: delay time between data to be transmitted.        
A first conventional example of such a spread spectrum communication systems is disclosed in Japanese Patent Laying-Open No. 9-55714 to implement a rapid communication by multiplexing data while preventing communications characteristics from deteriorating. This system serial-parallel converts data to be transmitted and applies a single spreading code sequence to a plurality of such data to provide spread-spectrum data and the results of the spreading are delayed by different delay times, respectively, and then combined and thus multiplexed.
FIG. 23 is a block diagram of a spreading and multiplexing circuit on a transmitting side in the spread spectrum communication systems of the first conventional example.
This spreading and multiplexing circuit is configured by a serial-parallel converter 16, a spreading code sequence generator 17, a multiplier 18, a delay unit 19, and a summation unit 20. Serial-parallel converter 16 serial-parallel converts data to be transmitted. Spreading code sequence generator 17 generates a spreading code sequence. Multiplier 18 receives from serial-parallel converter 16 a plurality of parallel data to be transmitted and multiplies the parallel data by a single, spreading code sequence generated by spreading code sequence generator 17, to provide spread spectrum data. Ddelay unit 19 delays a result of the multiplication of multiplier 18 by a respective, different delay time. Summation unit 20 adds all such results of the multiplication together to multiplex the same. Thus a plurality of data to be transmitted can have the spectrum spread by a single spreading code sequence and the results of the spreading can be delayed by different delay times, respectively, and then configured and thus be multiplexed.
Furthermore, a second conventional example is disclosed in Japanese Patent No. 2803237. It is a modulator modulating a plurality of data to be transmitted, each with a spreading code sequence corresponding to a single pseudo noise (or a spreading code sequence) offset (shifted) in phase, respectively, and thus providing spread spectrum data which are in turn matched in phase and thus added together for each chip and thus multiplexed.
FIG. 24 is a block diagram of a spreading and multiplexing circuit in a data communication transmitter of the second conventional example. In FIG. 24, the spreading and multiplexing circuit is configured by a sequence code generator 40, operation units 41(1) to 41(L), pipeline registers 42(1) to 42(L), and a delay shift register 43. Sequence code generator 40 generates a spreading code sequence, one chip at a time, in synchronization with a clock signal. Operation units 41(1) to 41(L) share a spreading code sequence generated by sequence code generator 40 and also receive L data to be transmitted 1-L, respectively. The initial-stage operation unit 41(1) receives “0” and the remaining operation units 41(2) to 41(L) each receive an output of the immediately preceding pipeline register. If data to be transmitted is “1”, the value of the spreading code sequence (a conversion “−1” for “0”) is added to “0”/a value output from the immediately preceding pipeline register. If data to be transmitted is “0”, then “0”/a value output from the immediately preceding pipeline register is output. Pipeline registers 42(1) to 42(L) receive the outputs of operation units 41(1) to 41(L), respectively, and shift in response to a clock signal to shift phase. Delay shift register 43 delays a spreading code sequence to generate a reference sequence signal.
In the spreading and multiplexing circuit of the first conventional example, however, the number of the multipliers and that of the delay units need to match a maximal number of signals in multiplexing, and furthermore the number of multipliers used and that of delay units used need to vary when that of signals in multiplexing varies. In the system disclosed in Japanese Patent Laying-Open No. 9-55714, a timing of multiplexing can be changed in operation and a number of signals in multiplexing can be switched to another implement multi-rate allowing a plurality of transmission rates to be selected, although the delay unit is required to provide a delay time varying dynamically.
Thus the spreading and multiplexing circuit of the first conventional example disadvantageously has a complicated circuit configuration and is controlled in a complicated manner. Furthermore in the spreading and multiplexing circuit of the first conventional example there exists a chip devoid of multiplexing by a predetermined number when it is powered on at the time when it starts operation from the initial status, such as when a transmission starts, and when a number of signals in multiplexing is switched to another during a transmission, for example at a boundary where the number is switched between a header and data. This contributes to establishment of correlation synchronization attributed to an inappropriate timing and erroneous detection of a correlation value required for a post-demodulation data decision from a result of an operation of a correlation value of a spread-spectrum waveform received by a receiver (a waveform sampled in response to a clock several times a chip rate) and a spreading code sequence. In other words, there is a high possibility that there occurs a capture of demodulation data position in a received signal at an inappropriate timing, which can introduce data error in demodulation. Disadvantageously the spreading and multiplexing circuit of the first conventional example can hardly address this deficiency.
The spreading and multiplexing circuit of the second conventional example cannot change the number of signals in multiplexing or the amount of shifting a phase of a spreading code sequence for its circuit configuration. It only allows communications with a designed, series of numbers of signals in multiplexing and a designed, series of amounts of phase-shifting and it cannot implement multi-rate.
Furthermore in the spreading and multiplexing circuit of the second conventional example if the number of data desired to be successively transmitted is larger than that of operation units and that of pipeline registers, each data to be transmitted needs to be input to an operation unit at a timing delayed to correspond to an amount of shifting of a phase of a spreading code sequence corresponding thereto. This requires a circuit serial-parallel converting the data to be transmitted, and delaying a timing of outputting the parallel data, by an amount of phase-shifting, and accordingly increases the scale of the circuit of interest. Furthermore, it is difficult to provide this serial-parallel conversion and delay circuit to accommodate changes in the number of signals in multiplexing and that of amounts of phase-shifting, which is another factor preventing the implementation of multi-rate.